1. Field of the Invention
The present invention relates to a semiconductor device and particularly to a semiconductor device manufacturing method including a process of forming a silicide layer on gate electrodes and drain/source regions of semiconductor devices using an SOI (Silicon on Insulator) substrate.
2. Description of the Related Art
There is an increasing demand for LSIs with low power consumption and high performance for product applications related to personal mobile communications. However, usual CMOS devices using a silicon substrate are increasing in power consumption due to becoming more highly integrated and higher in speed with circuit elements becoming finer in size, and hence it is desired that new low power devices with a new device structure be developed. In this situation, SOI devices using an SOI (Silicon On Insulator) substrate having an insulating film between a silicon substrate and a device area are expected to serve as low power consumption, high performance devices.
The SOI devices have a structure where a semiconductor substrate layer and a semiconductor layer (an SOI layer) formed over it are separated and insulated by a buried oxide film (BOX layer). By this means, insulating separation between adjacent elements can be easily achieved, and further because a parasitic thyristor is not formed via the semiconductor substrate layer, a latch-up phenomenon is prevented from occurring. Yet further, constructing transistors in the SOI layer is effective in suppressing the so-called short-channel effect that as transistors become finer, power consumption increases. Still further, because their junction capacitance is smaller than that of transistors of a bulk structure, transistors formed of the SOI structure can operate at higher speed. Since having many excellent characteristics as such, transistors of the SOI structure are expected to be able to achieve higher speed and lower power consumption as compared with conventional semiconductor elements formed in a bulk substrate.
The SOI devices are classified into partially depleted SOI (PD-SOI) and fully depleted SOI (FD-SOI) according to the thickness of the semiconductor layer (SOI layer). For the PD-SOI, a usual CMOS process for the bulk substrate can be used as it is, and thus the PD-SOI can be fabricated at lower cost than the FD-SOI. However, because the SOI layer of the PD-SOI is thick, so-called impact ionization causes holes to accumulate underneath channels. Thus, a kink effect occurs in current-voltage characteristics, which causes problems. In contrast, for the FD-SOI, the SOI layer is thin enough that this phenomenon does not occur. Further, because threshold voltages (Vt) can be set low without an increase in off leak current as compared with the PD-SOI, the FD-SOI has the advantage of being capable of operating at low voltages as well.
As such, the FD-SOI has many advantages, but the thickness of the SOI layer is usually as thin as 50 nm or less, hence causing an increase in parasitic resistance. In order to make transistors operate at high speed, it is important to reduce parasitic resistance. The salicide process that forms silicide layers of, e.g., cobalt silicide (CoSi2) or the like simultaneously, respectively on gate electrodes and drain/source regions is effective as a method to reduce the parasitic resistance of transistors.
An example of the conventional salicide process is shown below. First, a cobalt (Co) film of about 50 to 100 Å thickness is deposited by a sputter method entirely over an SOI substrate having gate electrodes and drain/source regions formed. Then, an RTA (Rapid Thermal Anneal) process at about 550° C. is performed. By this heat treatment, cobalt (Co) and silicon (Si) react, so that a cobalt monosilicide (CoSi) layer is formed in the surfaces of gate electrodes and of drain/source regions. Then, by cleaning with a sulfuric acid hydrogen peroxide mixture, an ammonia hydrogen peroxide mixture, or the like, unreacted cobalt (Co) deposited on the SOI substrate is removed. Thereafter, by further performing the RTA process at about 650° C. to 850° C., silicide layers of CoSi2 are respectively formed in the surfaces of gate electrodes and of drain/source regions.